STM32F303VE datasheet(29/184 Pages) STMICROELECTRONICS

29 / 184 page

DocID026415 Rev 4

29/184

STM32F303xD STM32F303xE

Functional overview

In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and

ALERT protocol management. They also have a clock domain independent from the CPU

clock, allowing the I2Cx (x=1,2,3) to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller.

Refer to Table 7 for the features available in I2C1, I2C2 and I2C3.

3.21

Universal synchronous/asynchronous receiver transmitter

(USART)

The STM32F303xD/E devices have three embedded universal synchronous/asynchronous

receiver transmitters (USART1, USART2 and USART3).

The USART interfaces are able to communicate at speeds of up to 9 Mbit/s.

They provide hardware management of the CTS and RTS signals, they support IrDA SIR

ENDEC, the multiprocessor communication mode, the single-wire half-duplex

communication mode and have LIN Master/Slave capability. The USART interfaces can be

served by the DMA controller.

Table 7. STM32F303xD/E I2C implementation

I2C features(1)

I2C1

I2C2

I2C3

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

1. X = supported.

STM32F303VE датащи(PDF) 29 Page - STMicroelectronics