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M34E04B датащи(PDF) 27 Page - STMicroelectronics |
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M34E04B датащи(HTML) 27 Page - STMicroelectronics |
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27 / 35 page ![]() DocID028428 Rev 1 27/35 M34E04B DC and AC parameters 34 Table 13. AC characteristics Symbol Parameter VCC < 2.2 V VCC ≥ 2.2 V Unit 100 kHz 400 kHz 1000 kHz Min. Max. Min. Max. Min. Max. fSCL fC Clock frequency 10 100 10 400 10 1000 kHz tHIGH tCHCL Clock pulse width high time 4000 - 600 - 260 - ns tLOW (1) tCLCH Clock pulse width low time 4700 - 1300 - 500 - ns tTIMEOUT (2) Detect clock low timeout 25 35 25 35 25 35 ms tR (3) tXH1XH2 SDA rise time - 1000 20 300 - 120 ns tF (3) tQL1QL2 SDA(out) fall time - 300 20 300 - 120 ns tSU:DAT tDXCH Data in setup time 250 - 100 - 50 - ns tHD:DI tCLDX Data in hold time 0 - 0 - 0 - ns tHD:DAT tCLQX Data out hold time 200 3450 200 900 0 350 ns tSU:STA (4) tCHDL Start condition setup time 4700 - 600 - 260 - ns tHD:STA tDLCL Stop condition hold time 4000 - 600 - 260 - ns tSU:STO tCHDH Stop condition setup time 4000 - 600 - 260 - ns tBUF tDHDL Time between Stop Condition and next Start Condition 4700 - 1300 - 500 - ns tW Write time - 5 - 5 - 5 ms tPOFF (3) Time ensuring a Reset when VCC drops below VPDR(min) 100 - 100 - 100 - µs tINIT (3) Time from VCC(min) to the first command 0-0- 0 - µs 1. Initiate clock stretching, which is an optional SMBus bus feature. 2. A timeout condition can only be ensured if SCL is driven low for tTIMEOUT(Max) or longer; then the M34E04B is set in Standby mode and is ready to receive a new START condition. If SCL is driven low for less than tTIMEOUT(Min), the M34E04B internal state remains unchanged. 3. Measured during characterization, not tested in production. 4. To avoid spurious START and STOP conditions, a minimum delay is placed between the falling edge of SCL and the falling or rising edge of SDA. |
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