M34E04B datasheet(17/35 Pages) STMICROELECTRONICS

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M34E04B

Device operation

Note:

The seven most significant bits of the device select code of a Random Read (in the 1st and

3rd bytes) must be identical.

3.8

Setting the write protection

There are four independent memory blocks, and each block may be independently

protected. The memory blocks are:

•

Block 0 = memory addresses 0x00 to 0x7F (decimal 0 to 127), page address = 0

•

Block 1 = memory addresses 0x80 to 0xFF (decimal 128 to 255), page address = 0

•

Block 2 = memory addresses 0x00 to 0x7F (decimal 0 to 127), page address = 1

•

Block 3 = memory addresses 0x80 to 0xFF (decimal 128 to 255), page address = 1

The device has three software commands for setting, clearing, or interrogating the write-

protection status.

•

SWPn: Set Write Protection for block n

•

CWP: Clear Write Protection for all blocks

•

RPSn: Read Protection status for block n

The level of write protection (set or cleared), that has been defined using these instructions,

remains defined even after a power cycle.

The DTICs of the SWP, CWP and RPS instructions are defined in Table 2.

3.8.1

Set and clear the write protection (SWPn and CWP)

If the software write protection has been set with the SWPn instruction, it may be cleared

again with a CWP instruction. SWPn acts on a single block as specified in the SWPn

command, but CWP clears the write protection for all blocks.

When decoded, SWPn and CWPn trigger a write cycle lasting tW (see Table 13).

The DTICs of the SWP and CWP instructions are defined in Table 2.

Figure 8. Setting the write protection

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