L9779WD datasheet(137/170 Pages) STMICROELECTRONICS

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L9779WD

Functional description

169

If a new read command is received while the current 4 up-stream communication is active,

the 16 bit up-stream on-going is completed and after the inter-frame bit it is sent the new 4

WR_CONFIG1, 2, 3, 4, 5, 6, 7, WR_RESP, WR_RESPTIME

CSB

: command selection bit - always '1'

C(5...0) : command bit

CD(7...0): command data bit

Writes the register CONFIG_REG1, 2, 3, 4, 5, 6, 7

Lock, unlock

CSB

: command selection bit - always '1'

C(5...0) : command bit

CD(7...0): command data bit

This command disables ("lock") writing of all configuration registers. The commands have

no relevant data as command data bit - they may be set to '1' or '0'.

The registers RESP and RESPTIME are not affected by LOCK command (i.e. they cannot

be locked)

Default state is configuration registers not locked.

The content of a lockable bit is valid both if the bit is locked or if it is unlocked. Writing data

to the bit is possible if the bit is unlocked; the new values become valid during execution of

the write command.

Table 65. WR_CONFIG1, 2, 3, 4, 5, 6, 7, WR_RESP, WR_RESPTIME

Command

CSB

C(5..0)

CD(7..0)

WR_CONFIG1

0 0 1 1 1 1

CONFIG1(7:0)

WR_CONFIG2

0 1 0 0 0 1

CONFIG2(7:0)

WR_CONFIG3

0 1 0 0 1 0

CONFIG3(7:0)

WR_CONFIG4

0 1 0 1 0 0

CONFIG4(7:0)

WR_CONFIG5

0 1 0 1 1 1

CONFIG5(7:0)

WR_CONFIG6

0 1 1 0 0 0

CONFIG6(7:0)

WR_CONFIG7

0 1 1 0 1 1

CONFIG7(7:0)

WR_RESP

1 0 0 1 0 0

RESP

WR_RESPTIME

1 1 0 0 0 0

WDA_RESPTIME

WR_CPS

1 1 0 0 1 1

CPS

Table 66. Lock, unlock

Command

CSB

C(5..0)

CD(7..0)

Lock

0 1 1 1 0 1

X X X X X X X X

Unlock

0 1 1 1 1 0

X X X X X X X X

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