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L9779WD датащи(PDF) 136 Page - STMicroelectronics |
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L9779WD датащи(HTML) 136 Page - STMicroelectronics |
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136 / 170 page ![]() Functional description L9779WD 136/170 DocID027452 Rev 5 Note: Pay attention to the fact that the LSB is always transmitted first. RD_DATA1, 2, 3, 4, 5, 6, 7 and 8 CSB : command selection bit - always '1' C(5...0) : command bit CD(7...0): command data bit READ_DATA1 initiates 4 upstream communications that transfer data block 1 that consists of the registers CONFIG_REG1, CONFIG_REG2, CONFIG_REG3 and CONFIG_REG4, transmitted exactly in this order. READ_DATA2 initiates 4 upstream communications that transfer data block 2 that consists of the registers CONFIG_REG5, CONFIG_REG6, CONFIG_REG7, not used, transmitted exactly in this order. READ_DATA3 initiates 4 upstream communications that transfer data block 3 that consists of the registers DIA_REG1, DIA_REG2, DIA_REG3 and DIA_REG4, transmitted exactly in this order. READ_DATA4 initiates 4 upstream communications that transfer data block 4 that consists of the registers DIA_REG5, DIA_REG6, DIA_REG7 and DIA_REG8, transmitted exactly in this order. READ_DATA5 initiates 4 upstream communications that transfer data block 5 that consists of the registers DIA_REG9, DIA_REG10, DIA_REG11 and IDENT_REG, transmitted exactly in this order. READ_DATA6 initiates 4 upstream communications that transfer data block 6 that consists of the registers WDA_QUERY, not used, STEP_CTN_H and STEP_CTN_L. READ_DATA7 initiates 4 upstream communications that transfer data block 7 that consists of the registers DIA_REG12, DIA_REG12, RESP, and WDA_RESPTIME. READ_DAT8 initiates 4 upstream communications that transfer data block 7 that consists of the registers WDA_RESPTIME, REQULO, REQUHI, RST_AB1_CNT. The command has no relevant data as command data bit - they may be set to '1' or '0'. Table 64. RD_DATA1, 2, 3, 4, 5, 6, 7 and 8 Command CSB C(5..0) CD(7..0) RD_DATA1 1 0 0 0 0 1 1 X X X X X X X X RD_DATA2 1 0 0 0 1 0 1 X X X X X X X X RD_DATA3 1 0 0 0 1 1 0 X X X X X X X X RD_DATA4 1 0 0 1 0 0 1 X X X X X X X X RD_DATA5 1 0 0 1 0 1 0 X X X X X X X X RD_DATA6 1 0 0 1 1 0 0 X X X X X X X X RD_DATA7 1 1 0 1 1 0 1 X X X X X X X X RD_DATA8 1 1 0 1 1 1 0 X X X X X X X X |
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