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L9779WD датащи(PDF) 134 Page - STMicroelectronics |
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L9779WD датащи(HTML) 134 Page - STMicroelectronics |
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134 / 170 page ![]() Functional description L9779WD 134/170 DocID027452 Rev 5 CLP, CLN VCL_low Differential input low detection level VCL_low= VCLP_low- VCLN_low --100 - - mV DIP, DIN VDIP, VDIN Input voltage range Not to be tested. It is an application note. 0.8 - 1.6 V VDIdiff Differential input voltage VDIdiff =|VDIP-VDIN| 150 - 450 mV VDIdiff Input voltage offset VDIdiff =0.5*(VCLP+VCLN) 1- 1.4 V Rcl Resistor between DIP and DIN - 100 - Ω Rpu_N Internal pull-up resistor - 100 200 400 kΩ Rpd_P Internal pull-down resistor - 100 200 400 kΩ VDI_high Differential input high detection level VDI_high= VDIP_high- VDIN_high -- - 100 mV VDI_low Differential input low detection level VDI_low= VDIP_low- VDIN_low --100 - - mV DO VDO_L DO output low level VDD_IO = 5 V or 3.3 V Isink current = 2 mA -- 0.5 V VDO_H DO output high level VSUP = 5 V or 3.3 V Isource current=2mA VDD_IO -0.5 -- V fDO Maximum frequency Tested by SCAN fCL/ 128 fCL/ 64 fCL/ 16 MHz EN ENL Low input level - -0.3 - 1.1 V ENH High input level - 2.3 - VDD 5+0.3 V VHYST Hysteresis - 0.1 - - V IIN Input current - - - 5 µA RPU Pull-up resistor - 50 - 250 kΩ Table 62. Time electrical characteristics (continued) Pin Symbol Parameter Test condition Min Typ Max Unit |
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