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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9779WD датащи(PDF) 130 Page - STMicroelectronics |
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L9779WD датащи(HTML) 130 Page - STMicroelectronics |
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130 / 170 page  Functional description L9779WD 130/170 DocID027452 Rev 5 Figure 79. Data frame diagram Upstream communication The serial data output [DO] is the synchronous serial data signal of the upstream channel. The polarity for [DO] is ‚normal polarity'- i.e. a low level bit at [DO] is stored in the µC as a logic ‚0', and a high level bit at [DO] is stored in the µC as a logic ‚1'. The serial data output is single-ended. The frequency is derived from CL by an internal divider to typ. fSDO = CL/64. It can be adjusted via MSC to fSDO = CL/16... CL/128. The time for a bit is TSDO = fSDO. Each upstream frame consists of 16 bit: 1 start bit, always '0' 4-bit-upstream address field (A[0..3] with LSB first) 8 bit data upstream data field (D[0..7] with LSB first) 1 upstream parity bit (with odd parity for the complete data frame) 2 fSDO stop bit, always '1'. Note: External pull-up resistor on SDO pin is required. Its value depends on MSC SDO bit rate. Table 60. Content of a data frame (transmitted LSB first) Bit Description Data selection bit 0 0-7 CONTR_REG1(LSB…MSB) 8-15 CONTR_REG2(LSB…MSB) 16-23 CONTR_REG3(LSB…MSB) 24-29 CONTR_REG4(LSB…MSB) |
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