L9779WD datasheet(127/170 Pages) STMICROELECTRONICS

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L9779WD

Functional description

169

6.18

Serial interface

The L9779WD offers the possibility to communicate with a µC using the MicroSecond

Channel (MSC).

The serial communication is used:



to set the parameter



to read diagnosis



to activate, to deactivate and to use the low side drivers



to activate test mode (ST reserved).

6.18.1

MSC interface

Communication with the microcontroller is done via MSC i.e.MicroSecond Channel;

equivalent to µsec-bus 2nd generation.

Downstream communication is data or command sent by µC and received by L9779WD.

Upstream communication is data sent by the L9779WD and received by µC.

The MicroSecond Channel (MSC) interface provides a serial communication link typically

used to connect peripheral devices with a micro controller. The serial communication link is

built up by a fast synchronous downstream channel (with differential inputs and differential

clock) and a slow synchronous upstream channel.

Differential inputs for downstream data are pins [DIP] and [DIN]; the differential input signal

[DIP]-[DIN] is referred to as DI. The clock pins are [CLP] and [CLN], the differential clock

[CLP]-[CLN] is referred to as CL. There is an internal resistor between pins [DIP] and [DIN] -

and between [CLP] and [CLN].

There is one input for chip select at pin [EN], and one output for upstream data at pin [DO].

L9779WD always is the slave in this communication link. These pins are single-ended.

Multiple power devices with MSC on downstream are possible. Downstream device is

selected by EN.

MSC uses normal polarity for DI, CLK, and DO: a logic '1' is a 'high level' and a logic '0' is a

'low level'.

MSC uses inverted polarity for EN: a logic '1' is a 'low level' and a logic '0' is a 'high level'.

By this way it is possible to drive multiple power devices with shared CL and DI lines and

individual EN signal.

The maximum downstream clock rate is CL = 40MHz. Upstream is done with a lower clock

rate fSDO, selectable by the microcontroller; after a reset the upstream clock rate is

fSDO = CL/64.

The upstream clock is synchronous with CL since it is derived from a clock divider.

Therefore the CL signal must always be running independently whether a downstream

transmission is running or not.

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