1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

G

H

J

Dx_SEL

VDD

DA0(n)

DA1(n)

DA2(n)

DA3(p)

DA3(n)

DC0(n)

DC0(p)

GND

DA0(p)

DA1(p)

DA2(p)

OE

DB0(p)

DB0(n)

AUX_SEL

GND

DC1(n)

DC1(p)

DB1(p)

DB1(n)

DC2(p)

DC2(n)

DB2(p)

DB2(n)

DC3(n)

DC3(p)

DB3(p)

DB3(n)

GND

GND

AUXC(n)

AUXC(p)

HPDB

GND

DDCCLK_B AUXB(p)

GND

DDCCLK_A

AUXA(p)

HPDC

HPDA

DDCCLK_C

VDD

DDCDAT_B

AUXB(n)

AUXA(n)

HD3SS214

www.ti.com

SLAS907 – DECEMBER 2015

5 Pin Configuration and Functions

ZQE Package

50-ball (µBGA)

Top View

Pin Functions

PIN

I/O

NO.

NAME

A1

Dx_SEL

Control I

High Speed Port Selection Control Pins

A2, J4

VDD

Supply

3.3 V Positive power supply voltage

A4

DA0(n)

I/O

Port A, Channel 0, High Speed Negative Signal

A5

DA1(n)

I/O

Port A, Channel 1, High Speed Negative Signal

A6

DA2(n)

I/O

Port A, Channel 2, High Speed Negative Signal

A8

DA3(p)

I/O

Port A, Channel 3, High Speed Positive Signal

A9

DA3(n)

I/O

Port A, Channel 3, High Speed Negative Signal

B1

DC0(n)

I/O

Port C, Channel 0, High Speed Negative Signal

B2

DC0(p)

I/O

Port C, Channel 0, High Speed Positive Signal

B3, C8, G2,

GND

Supply

Ground

G8, H4, H7

B4

DA0(p)

I/O

Port A, Channel 0, High Speed Positive Signal

B5

DA1(p)

I/O

Port A, Channel 1, High Speed Positive Signal

B6

DA2(p)

I/O

Port A, Channel 2, High Speed Positive Signal

(1)

The high speed data ports incorporate 20-k

Ω pull down resistors that are switched in when a port is not selected and switched out when

the port is selected.

Copyright © 2015, Texas Instruments Incorporated

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