ADC0804LCWMXSLASHNOPB datasheet(48/56 Pages) TI1

48 / 56 page

ADC0801, ADC0802, ADC0803, ADC0804, ADC0805

SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015

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10 Power Supply Recommendations

Precautions should be taken to insure that the power supply for the integrated circuit never becomes reversed in

polarity or that the unit is not inadvertently installed backwards in a test socket as an unlimited current surge

through the resulting forward diode within the device could cause fusing of the internal conductors and result in a

destroyed unit.

Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise. A

low-inductance, low-ESR tantalum bypass capacitor should be used close to the converter VCC pin, and a 10-µF

is recommended. If an unregulated voltage is available in the system, a separate 5-V voltage regulator for the

converter (and other analog circuitry) will greatly reduce digital noise on the VCC supply.

11 Layout

11.1 Layout Guidelines

All logic signal wires and leads should be grouped and kept as far away as possible from the analog signal

leads. Exposed leads to the analog inputs can cause undesired digital noise and 60-Hz pickup. Shielded leads

for the analog inputs may be required in sensitive applications. A single-point analog ground should be used that

is also separated from the logic ground points. The power supply bypass capacitor should be returned to digital

ground. Any VREF/2 bypass capacitors, analog input filter capacitors, or input signal shielding should be returned

to the analog ground point. A test for proper grounding is to measure the zero error of the ADC converter. Zero

errors in excess of 1/4 LSB is generally traceable to improper PCB layout and/or wiring.

To minimize potential offset issues, TI recommends to route the signal traces differentially next to each other so

that they will see the same thermal gradients and the same number of feedthroughs. Furthermore, inductance is

determined by the size of the loop of current. Providing a path for return currents next to the signal trace will

reduce the inductance. A solid ground plane is very advantageous in this regard. Ensure to minimize the loop

area formed by the bypass capacitor connection between VCC and ground. The ground pin should be connected

to the PCB ground plane at the pin of the device.

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ADC0804LCWMX/NOPB датащи(PDF) 48 Page - Texas Instruments