ADC0804LCWMXSLASHNOPB datasheet(35/56 Pages) TI1

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ADC0801, ADC0802, ADC0803, ADC0804, ADC0805

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SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015

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Port A and the ADC0801 are at port address E4

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Port B is at port address E5

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Port C is at port address E6

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PPI control word port is at port address E7

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Program Counter automatically goes to ADDR:3C3D upon acknowledgment of an interrupt from the ADC0801

9.2.4 Multiple ADC Converters in a Z-80 Interrupt Driven Mode

In data acquisition systems where more than one ADC converter (or other peripheral device) will be interrupting

pro- gram execution of a microprocessor, there is obviously a need for the CPU to determine which device

requires servicing. Figure 47 and the accompanying software is a method of determining which of 7 ADC0801

converters has completed a conversion (INTR asserted) and is requesting an interrupt. This circuit allows starting

the ADC converters in any sequence, but will input and store valid data from the converters with a priority

sequence of ADC 1 being read first, ADC 2 second, etc., through ADC 7 which would have the lowest priority for

data being read. Only the converters whose INT is asserted will be read.

The key to decoding circuitry is the DM74LS373, 8-bit D type flip-flop. When the Z-80 acknowledges the

interrupt, the program is vectored to a data input Z-80 subroutine. This subroutine will read a peripheral status

word from the DM74LS373 which contains the logic state of the INTR outputs of all the converters. Each

converter which initiates an interrupt will place a logic "0" in a unique bit position in the status word and the

subroutine will determine the identity of the converter and execute a data read. An identifier word (which

indicates which ADC the data came from) is stored in the next sequential memory location above the location of

the data so the program can keep track of the identity of the data entered.

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