ADC0804LCWMXSLASHNOPB datasheet(23/56 Pages) TI1

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SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015

Table 2. Design Parameters

PARAMETER

EXAMPLE VALUE

ADC clock frequency, FCLK

640 KHz

Input source resistance, RIN

100

9.2.1.2 Detailed Design Procedure

9.2.1.2.1

Analog Differential Voltage Inputs and Common-Mode Rejection

This ADC has additional applications flexibility due to the analog differential voltage input. The VIN(−) input (pin 7)

can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also

useful in 4 mA–20 mA current loop conversion. In addition, common-mode noise can be reduced by use of the

differential input.

The time interval between sampling VIN(+) and VIN(−) is 4-1/2 clock periods. The maximum error voltage due to

this slight time difference between the input voltage samples is given by:

where

•

∆Ve is the error voltage due to sampling delay

•

VP is the peak value of the common-mode voltage

•

fcm is the common-mode frequency

(1)

As an example, to keep this error to 1/4 LSB (

∼5 mV) when operating with a 60 Hz common-mode frequency,

fcm, and using a 640 kHz ADC clock, fCLK, would allow a peak value of the common-mode voltage, VP, which is

given by:

(2)

(3)

which gives VP–1.9 V.

The allowed range of analog input voltages usually places more severe restrictions on input common-mode noise

levels.

An analog input voltage with a reduced span and a relatively large zero offset can be handled easily by making

use of the differential input (see Reference Voltage).

9.2.1.2.2

Analog Inputs — Input Current

9.2.1.2.2.1

Input Bypass Capacitors

Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output

resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with

the VIN(+) input voltage at full-scale. For continuous conversions with a 640 kHz clock frequency with the VIN(+)

input at 5V, this DC current is at a maximum of approximately 5 µA. Therefore, bypass capacitors should not be

used at the analog inputs or the VREF/2 pin for high resistance sources (> 1 kΩ). If input bypass capacitors are

necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the detrimental

effects of the voltage drop across this input resistance, which is due to the average value of the input current,

can be eliminated with a full-scale adjustment while the given source resistor and input bypass capacitor are both

in place. This is possible because the average value of the input current is a precise linear function of the

differential input voltage.

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