ADC0804LCWM datasheet(28/56 Pages) TI1

28 / 56 page

ADC0801, ADC0802, ADC0803, ADC0804, ADC0805

SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015

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9.2.1.2.6

Restart During a Conversion

If the ADC is restarted (CS and WR go low and return high) during a conversion, the converter is reset and a

new conversion is started. The output data latch is not updated if the conversion in process is not allowed to be

completed, therefore the data of the previous conversion remains in this latch. The INTR output simply remains

at the “1” level.

9.2.1.2.7

Continuous Conversions

For operation in the free-running mode an initializing pulse should be used, following power up, to ensure circuit

operation. In this application, the CS input is grounded and the WR input is tied to the INTR output. This WR and

INTR node should be momentarily forced to logic low following a power-up cycle to ensure operation.

9.2.1.2.8

Driving the Data Bus

This MOS ADC, like MOS microprocessors and memories, will require a bus driver when the total capacitance of

the data bus gets large. Other circuitry, which is tied to the data bus, will add to the total capacitive loading, even

in Tri-state (high impedance mode). Backplane bussing also greatly adds to the stray capacitance of the data

bus.

There are some alternatives available to the designer to handle this problem. Basically, the capacitive loading of

the data bus slows down the response time, even though DC specifications are still met. For systems operating

with a relatively slow CPU clock frequency, more time is available in which to establish proper logic levels on the

bus and therefore higher capacitive loads can be driven (see typical characteristics curves).

At higher CPU clock frequencies time can be extended for I/O reads (and/or writes) by inserting wait states

(8080) or using clock extending circuits (6800).

Finally, if time is short and capacitive loading is high, external bus drivers must be used. These can be Tri-state

buffers (low power Schottky such as the DM74LS240 series is recommended) or special higher drive current

products which are designed as bus drivers. High current bipolar bus drivers with PNP inputs are recommended.

9.2.1.2.9

Wiring and Hook-Up Precautions

Standard digital wire wrap sockets are not satisfactory for breadboarding this ADC converter. Sockets on PCBs

can be used and all logic signal wires and leads should be grouped and kept as far away as possible from the

analog signal leads. Exposed leads to the analog inputs can cause undesired digital noise and hum pickup,

therefore shielded leads may be necessary in many applications.

A single point analog ground that is separate from the logic ground points should be used. The power supply

bypass capacitor and the self-clocking capacitor (if used) should both be returned to digital ground. Any VREF/2

bypass capacitors, analog input filter capacitors, or input signal shielding should be returned to the analog

ground point. A test for proper grounding is to measure the zero error of the ADC converter. Zero errors in

excess of 1/4 LSB can usually be traced to improper board layout and wiring (see Zero Error for measuring the

zero error).

9.2.2 Multiple ADC0801 Series to MC6800 CPU Interface

To transfer analog data from several channels to a single microprocessor system, a multiple converter scheme

presents several advantages over the conventional multiplexer single-converter approach. With the ADC0801

series, the differential inputs allow individual span adjustment for each channel. Furthermore, all analog input

channels are sensed simultaneously, which essentially divides the total system servicing time of the

microprocessor by the number of channels, because all conversions occur simultaneously. This scheme is

shown in Figure 40.

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