ADC0804LCWM datasheet(27/56 Pages) TI1

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CLK

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10 k

ADC0801, ADC0802, ADC0803, ADC0804, ADC0805

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SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015

9.2.1.2.4.3

Adjusting for an Arbitrary Analog Input Voltage Range

If the analog zero voltage of the ADC is shifted away from ground (for example, to accommodate an analog input

signal that does not go to ground) this new zero reference should be properly adjusted first. A VIN(+) voltage that

equals this desired zero reference plus 1/2 LSB (where the LSB is calculated for the desired analog span, 1

LSB=analog span/256) is applied to pin 6 and the zero reference voltage at pin 7 should then be adjusted to just

obtain the 00HEX to 01HEX code transition.

The full-scale adjustment should then be made (with the proper VIN(−) voltage applied) by forcing a voltage to the

VIN(+) input which is given by:

where

•

VMAX = The high end of the analog input range

•

VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.)

(4)

The VREF/2 (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the

adjustment procedure

9.2.1.2.5

Clocking Option

The clock for the ADC can be derived from the CPU clock or an external RC can be added to provide self-

clocking. The CLK IN (pin 4) makes use of a Schmitt trigger as shown in Figure 35.

Figure 35. Self-Clocking the ADC

Heavy capacitive or DC loading of the clock R pin should be avoided as this will disturb normal converter

operation. Loads less than 50 pF, such as driving up to 7 ADC converter clock inputs from a single clock R pin of

1 converter, are allowed. For larger clock line loading, a CMOS or low power TTL buffer or PNP input logic

should be used to minimize the loading on the clock R pin (do not use a standard TTL buffer).

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