L9663 datasheet(27/104 Pages) STMICROELECTRONICS

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L9663

Satellite interface

103

3.3.1

PSI5 receive register

This module includes the sensor data storage and diagnostic.

Basic features:



Storage of Sensor data



Error handling

Figure 13. Block diagram of incoming data buffer

PSI5 Receive Register

The transceiver IC has a PSI5 Receive Register for each PSI5 transceiver.

Each PSI5 Receive Register can store up to 28Bit data and up to 3Bit error check (CRC or

parity) for each of the incoming frames. According to the PSI5 powertrain substandard, up to

6 frames can be sent between two synchronous pulses. For every frame, a frame

configuration register is available which defines:



Data Region 8 … 28 bit



CRC or Parity Bit (3 or 1 bit)

Depending on the desired configuration (SPI bit CRC_CK of GCR1 register), the parity/CRC

bits handling can be done in the following ways:



Parity/CRC bits are generated by the sensor; the transceiver IC simply passes

data+parity/CRC bits to the μC via SPI and the μC performs parity/CRC check



Parity/CRC bits are calculated by the transceiver IC and in case of a correct parity

bit/checksum, the payload of the frame is stored in the receive buffer; otherwise, if the

CRC calculation shows a wrong result, the Parity Error code is stored.

The SPI register bit CRC_CK is valid for all sensors of both interfaces.

After all bits have been received the data will be transmitted into the corresponding part of

the receive buffer.

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