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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN9730 датащи(PDF) 20 Page - Microchip Technology |
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LAN9730 датащи(HTML) 20 Page - Microchip Technology |
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20 / 222 page  LAN9730/LAN9730i DS00001946A-page 20 2012-2015 Microchip Technology Inc. TABLE 2-4: MISCELLANEOUS PINS Num Pins Name Symbol Buffer Type Description 1 PHY Select PHY_SEL IS (PD) Selects whether to use the internal Ethernet PHY or the external PHY connected to the MII port. 0 = Internal PHY is used. 1 = External PHY is used. Note: When in External PHY Mode, the internal PHY is placed into general power down after a POR. Refer to Section 4.6, "10/100 Internal Ethernet PHY" for details. 1 System Reset nRESET IS (PU) This active-low pin allows external hardware to reset the device. Note: This pin may be used to signal PME_CLEAR when PME Mode of operation is in effect. Refer to Chapter 5.0, "PME Operation" for additional information. 1 Ethernet Full-Duplex Indicator LED nFDX_LED OD12 (PU) This pin is driven low (LED on) when the Ethernet link is operating in Full-Duplex mode. General Pur- pose I/O 8 GPIO8 IS/O12/ OD12 (PU) This General Purpose I/O pin is fully programma- ble as either a push-pull output, an open-drain output or a Schmitt-triggered input. Note: This pin may be used to signal PME when External PHY and PME Modes of operation are in effect. Refer to Chapter 5.0, "PME Operation" for additional information. Note: By default this pin is configured as a GPIO. |
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