LAN9730 datasheet(9/222 Pages) MICROCHIP

9 / 222 page

 2012-2015 Microchip Technology Inc.

DS00001946A-page 9

LAN9730/LAN9730i

1.2.8

TAP CONTROLLER

IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes.

The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface consists of five

pins (TDO, TDI, TCK, TMS, and nTRST) and includes a state machine, data register array and an instruction register.

The JTAG pins are described in Table 2-3, “JTAG Pins”. The JTAG interface conforms to the IEEE Standard 1149.1 -

1990 Standard Test Access Port (TAP) and Boundary-Scan Architecture.

All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into

the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge.

The JTAG logic is reset via Power on Reset (POR) or when the nTRST pin is asserted active-low.

The implemented IEEE 1149.1 instructions and their op codes are shown in Table 1-1.

1.2.9

CONTROL AND STATUS REGISTERS (CSR)

LAN9730/LAN9730i’s functions are controlled and monitored by the host via the Control and Status Registers (CSRs).

This register space includes registers that control and monitor the USB controller, as well as elements of overall system

operation (System Control and Status Registers - SCSRs), the MAC (MAC Control and Status Registers - MCSRs), and

the PHY (accessed indirectly through the MAC via the MII_ACCESS and MII_DATA registers). The CSR may be

accessed via the USB Vendor Commands (REGISTER READ/REGISTER WRITE). Refer to Section 4.3.3, "USB Ven-

dor Commands" for more information.

1.2.10

RESETS

LAN9730/LAN9730i supports the following system reset events:

• Power on Reset (POR)

• Hardware Reset Input Pin Reset (nRESET)

• Lite Reset (LRST) (Does not affect the UDC)

• Software Reset (SRST)

• USB Reset

The device supports the following module level reset events:

• Ethernet PHY Software Reset (PHY_RST)

• nTRST Pin Reset for Tap Controller

1.2.11

TEST FEATURES

Read/write access to internal SRAMs is provided via the CSRs. JTAG-based USB BIST is available. Full internal scan

and At Speed scan are supported.

TABLE 1-1:

IEEE 1149.1 OP CODES

Instruction

Op Code

Comment

Bypass

111111b

Mandatory Instruction

Sample/Preload

000100b

Mandatory Instruction

EXTEST

000001b

Mandatory Instruction

HIGHZ

000011b

Optional Instruction

IDCODE

001010b

Optional Instruction

Note:

The JTAG device ID is 00091445h.

Note:

All digital I/O pins support IEEE 1149.1 operation. Analog pins and the XI/XO pins do not support IEEE

1149.1 operation.

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