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LAN9730 датащи(PDF) 56 Page - Microchip Technology

номер детали LAN9730
подробное описание детали  High-Speed Inter-Chip USB 2.0 to 10/100 Ethernet Controller
PDF  222 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9730 датащи(HTML) 56 Page - Microchip Technology

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LAN9730/LAN9730i
DS00001946A-page 56
 2012-2015 Microchip Technology Inc.
4.4.2.6
TX Status Format
After an Ethernet frame is transmitted, the TLI returns the TX Status Word to the FCT, as illustrated in Table 4-44. The
contents of the TX Status Word is used for statistics generation and interrupt status creation. Refer to Section 4.3.1.7,
"Statistics" and Section 6.3.2, "Interrupt Status Register (INT_STS)" for further details.
TABLE 4-44:
TX STATUS WORD FORMAT
Bits
Description
31:16
RESERVED
15
Error Status (ES)
When set, this bit indicates that the TLI has reported an error. This bit is the logical OR of bits 11, 10, 9,
8, 2, 1 in this status word.
14:12
RESERVED
11
Loss of Carrier
When set, this bit indicates the loss of carrier during transmission.
10
No Carrier
When set, this bit indicates that the carrier signal from the transceiver was not present during transmis-
sion.
9
Late Collision
When set, indicates that the packet transmission was aborted after the collision window of 64 bytes.
8
Excessive Collisions
When set, this bit indicates that the transmission was aborted after 16 collisions while attempting to
transmit the current packet.
7
RESERVED
6:3
Collision Count
This counter indicates the number of collisions that occurred before the packet was transmitted. It is not
valid when Excessive Collisions (bit 8) is also set.
2
Excessive Deferral
If the deferred bit is set in the Control register, the setting of the Excessive Deferral bit indicates that the
transmission has ended because of a deferral of over 24288 bit times during transmission.
1
Underrun Error
When set, this bit indicates that the transmitter aborted the associated frame because of an underrun
condition on the TX Data FIFO. TX Underrun will cause the assertion of the TDFU flag in the Interrupt
Status Register (INT_STS) and the interrupt Endpoint.
0
Deferred
When set, this bit indicates that the current packet transmission was deferred.



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