BC3770 datasheet(5/45 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

BC3770

INTB

Output

Logic Output for Interrupt

An open-drain output with an external pull-up resistor, 200 k

, to the system I/O

supply. Active-low when status change on interrupt registers occurs.

C1, D1

Switching Node

Connect a 1.0

H inductor. The two LX pins must be connected together

externally.

NOBAT

Input

Logic Input for Battery

Presence Detection

Connect the pin to VF or ID pin on the battery cell. It has an internal pull-up

resistance, 300 k

 typ, to the VL. If a logic-high threshold is detected on the pin,

the charging is suspended immediately. If this pin is not used, connect it to

ground.

GND

Ground

Device Ground

Must be connected to the system ground.

BATREG

Battery + Terminal Sensing

Connect to positive terminal of battery cell as close as possible.

C5, D5, E5

CHGOUT

Output

Battery Charger Output

These pins must be connected together externally. Bypass with a 4.7

F/10 V or

higher to ground.

CHGENB

Input

Charger Enable Logic Input

Logic-low to enable charger. Logic-high to disable the charger, not to disable

buck converter. It has an internal 300 k

 resistance to ground. If this pin is not

used, leave it open or connect it to ground. The serial interface, I2C, is still

available in CHGENB = High.

SHDNB

Input

Logic Input for Disabling I2C

Interface

If there is no valid input source, logic-low is to put the I2C interface into Disabled

mode to reduce the idle current as low as possible. In the Shutdown mode, I2C

interface is not available but the Q4 FET is kept ON. A valid power source on

VBUS is able to overwrite to wake-up the device for Charge mode even in

SHDNB = Low. This pin is not effective as long as a valid input power source is

present.

This pin has an internal pull-down resistance, 300 k

 typ. If this pin is not used,

tie it to the system I/O supply rail or an appropriate rail to reduce idle current as

low as possible.

D4, E3, E4

VSYS

Output

System Supply Output

VSYS is the power supply for the system load. When a valid power source at

VBUS is attached, VSYS is regulated at 3.6 V until the BATREG hits the

threshold of VSYS_MIN x RDS(on)_Q4. When the +Terminal on the battery cell is

regulated at VBATREG, the VSYS output is regulated to the IFAST_CHG x

RDS(on)_Q4 above BATREG. Bypass with a 10 F/10 V ceramic capacitor to

ground.

E1, E2

PGND

Ground

Power Ground for the Buck

Converter

The two PGND pins must be connected together externally.

Table 2. BC3770 Pin Definitions (continued)

Pin Name

Function

Formal Name

Definition

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