LIS3DETR datasheet(35/46 Pages) STMICROELECTRONICS

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LIS3DE

8.17

OUT_Y (2Bh)

Y-axis acceleration data. The value is expressed in two’s complement with 8-bit data

representation left-justified.

8.18

OUT_Z (2Dh)

Z-axis acceleration data. The value is expressed in two’s complement with 8-bit data

representation left-justified.

8.19

FIFO_CTRL_REG (2Eh)

8.20

FIFO_SRC_REG (2Fh)

Table 43. FIFO_CTRL_REG register

FM1

FM0

FTH4

FTH3

FTH2

FTH1

FTH0

Table 44. FIFO_CTRL_REG register description

FM [1:0]

FIFO mode selection. Default value: 00 (see

Table 45)

Trigger selection. Default value: 0

0: trigger event linked to trigger signal on INT1

1: trigger event linked to trigger signal on INT2

FTH [4:0]

Default value: 0

Table 45. FIFO mode configuration

FM1

FM0

Self-test mode

Bypass mode

FIFO mode

Stream mode

Stream-to-FIFO mode

Table 46. FIFO_SRC_REG register

WTM

OVRN_FIFO

EMPTY

FSS4

FSS3

FSS2

FSS1

FSS0

Table 47. FIFO_SRC_REG register description

WTM

WTM bit is set high when FIFO content exceeds watermark level

OVRN_FIFO

OVRN bit is set high when FIFO buffer is full; this means that the FIFO buffer

contains 32 unread samples. At the following ODR a new sample set replaces the

oldest FIFO value. The OVRN bit is set to 0 when the first sample set has been read

EMPTY

EMPTY flag is set high when all FIFO samples have been read and FIFO is empty

FSS [4:0]

FSS [4:0] field always contains the current number of unread samples stored in the

FIFO buffer. When FIFO is enabled, this value increases at ODR frequency until the

buffer is full, whereas, it decreases every time one sample set is retrieved from FIFO

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