LIS3DETR datasheet(22/46 Pages) STMICROELECTRONICS

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Digital interfaces

LIS3DE

22/46

DocID023719 Rev 3

6.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the START condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a START condition with its address. If they match, the device considers itself

addressed by the master.

The slave address (SAD) associated to the LIS3DE is 010100xb. The SDO/SA0 pad can be

used to modify the least significant bit of the device address. If the SA0 pad is connected to

a voltage supply, LSB is ‘1’ (address 0101001b) or, if the SA0 pad is connected to ground,

the LSB value is ‘0’ (address 0101000b). This solution permits two different accelerometers

to be connected and addressed to the same I2C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver

which has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded inside the LIS3DE behaves like a slave device and the following protocol

must be adhered to. After the START condition (ST) a slave address is sent, once a slave

acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7

LSB represent the actual register address while the MSB enables address auto increment. If

the MSB of the SUB field is ‘1’, the SUB (register address) is automatically increased to

allow multiple data read/write.

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write),

the master transmits to the slave with direction unchanged. Table 12 explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 12. SAD+Read/Write patterns

Command

SAD[6:1]

SAD[0] = SA0

R/W

SAD+R/W

Read

010100

01010001 (51h)

Write

010100

01010000 (50h)

Read

010100

01010011 (53h)

Write

010100

01010010 (52h)

Table 13. Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

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