4.2 I2C Event Buffer Interface

4.2.1 Introduction

The event buffer I2C interface provides an event-driven, packetized communication system describing newly qualified events generated

by the capacitive sensing input engine.

The interface provides access to a first-in-first-out buffer of data packets. When the sensing engine generates these packets and push-

es them onto the buffer. The interface then signals a host to indicate that one or more packets are available in the buffer by activating

the event buffer interrupt pin.

The interrupt pin is defined as active-low and operates as a push-pull digital output.

The host reads the packets through an I2C interface, with the host acting as an I2C master. Once all packets have been fully transmit-

ted across the I2C interface, the event buffer interrupt pin is de-activated. The device will remain in active mode until no packets remain

in the buffer, even if no sensors have been qualified as active for the period of time defined by the active mode scan period and the

counts before sleep value.

4.2.2 Packet Retrieval

Event buffer access mode enables the host to retrieve host data structures from the device using a master read transaction. Transfers

in this mode should be made in 3-byte multiples to retrieve the entire event buffer structure.

Once the host reads the last byte of one event, that event is popped from the buffer. If only a part of the event is read, the event will

stay in the buffer and will be transmitted again by the device during the next read.

If the event buffer is read when no events have been pushed into the buffer for access, the bytes retrieved during a master read trans-

action across I2C will return 3 bytes of 0xFF padding.

If the interrupt pin goes active during a transaction where the transmission of these 3 bytes of padding are being sent, the 3 bytes of

padding will complete their transfer before a valid event will transmit.

If the I2C master sends a stop condition on the bus before the entire three-byte packet has been read, the device will not pop the pack-

et from its internal buffer. Instead, the I2C state machine will reset, and the next transaction will begin with the first byte of the same

event that was being read in the previous, prematurely-terminated transaction.

The I2C event buffer has a depth of 22 events. If the host does not read events promptly after seeing the interrupt pin go active, there is

the possibility of a buffer overflow. In the event of an overflow, the I2C engine will discard the oldest events first.

New I2C packets will only be generated at the active mode sample rate, and so the buffer will only fill at a maximum of 12 packets (in

the case of 12 simultaneous touch/releases) per sample period. If the host runs the I2C bus at 400kHz and reads packets as soon as

the interrupt pin activates, all packets can be read from the buffer in 1 to 2 ms, which is faster than the rate at which a new active mode

scan sequence can complete.

The configuraion profile includes an I2C timeout register. When enabled, this register configures the maximum duration at which pack-

ets will be stored in the I2C buffer without being read from the host. If the interrupt pin is allowed to remain active for the duration de-

fined by the timeout register, the I2C buffer will be flushed and the interrupt pin will deactivate. This feature is useful in applications

where it is not desireable to have the device remain in active mode indefinitely.

CPT112S Data Sheet

Functional Description

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