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CPT112S датащи(PDF) 7 Page - Silicon Laboratories |
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CPT112S датащи(HTML) 7 Page - Silicon Laboratories |
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7 / 35 page ![]() 3.1.3 Reset and Supply Monitor Table 3.3. Reset and Supply Monitor Parameter Symbol Test Condition Min Typ Max Unit VDD Supply Monitor Threshold VVDDM Reset Trigger 1.7 1.75 1.8 V VWARN Early Warning 1.8 1.85 1.9 V Power-On Reset (POR) Monitor Threshold VPOR Rising Voltage on VDD — 1.75 — V Falling Voltage on VDD 0.75 1.0 1.3 V VDD Ramp Time tRMP Time to VDD ≥ 1.8 V — — 3 ms RST Low Time to Generate Reset tRSTL 15 — — µs Boot Time1 tboot 1 sensor — 25 — ms 2 sensors — 40 — ms 3 sensors — 55 — ms 4 sensors — 70 — ms 5 sensors — 85 — ms 6 sensors — 100 — ms 7 sensors — 115 — ms 8 sensors — 130 — ms 9 sensors — 145 — ms 10 sensors — 160 — ms 11 sensors — 175 — ms 12 sensors — 200 — ms Note: 1. Boot time is defined as the time from a power-on reset or /RST pin release until the first capacitive sense scan begins. 3.1.4 Configuration Memory Table 3.4. Configuration Memory Parameter Symbol Test Condition Min Typ Max Units Endurance (Write/Erase Cycles) NWE 20 k 100 k — Cycles Note: 1. Data Retention Information is published in the Quarterly Quality and Reliability Report. CPT112S Data Sheet Electrical Specifications silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.1 | 6 |
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