ATmega16 datasheet(161/315 Pages) ATMEL

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ATmega16(L)

2466E–AVR–10/02

• Bit 0 – UCPOL: Clock Polarity

This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous

mode is used. The UCPOL bit sets the relationship between data output change and

data input sample, and the synchronous clock (XCK).

USART Baud Rate Registers –

UBRRL and UBRRH

The UBRRH Register shares the same I/O location as the UCSRC Register. See the

“Accessing UBRRH/ UCSRC Registers” on page 155 section which describes how to

access this register.

• Bit 15 – URSEL: Register Select

This bit selects between accessing the UBRRH or the UCSRC Register. It is read as

zero when reading UBRRH. The URSEL must be zero when writing the UBRRH.

• Bit 14:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit

must be written to zero when UBRRH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the

four most significant bits, and the UBRRL contains the 8 least significant bits of the

USART baud rate. Ongoing transmissions by the transmitter and receiver will be cor-

rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of

the baud rate prescaler.

Table 67. UCPOL Bit Settings

UCPOL

Transmitted Data Changed (Output of

TxD Pin)

Received Data Sampled (Input on

RxD Pin)

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

Bit

1514

1211

URSEL

–

UBRR[11:8]

UBRRH

UBRR[7:0]

UBRRL

765

432

Read/Write

R/W

Initial Value

000

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