ATmega16 datasheet(123/315 Pages) ATMEL

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123

ATmega16(L)

2466E–AVR–10/02

Note:

1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the

compare match is ignored, but the set or clear is done at TOP. See “Phase Correct

PWM Mode” on page 118 for more details.

• Bit 2:0 – CS22:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see

Table 54.

Timer/Counter Register –

TCNT2

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes)

the compare match on the following timer clock. Modifying the counter (TCNT2) while

the counter is running, introduces a risk of missing a compare match between TCNT2

and the OCR2 Register.

Table 53. Compare Output Mode, Phase Correct PWM Mode(1)

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on compare match when up-counting. Set OC2 on compare

match when downcounting.

Set OC2 on compare match when up-counting. Clear OC2 on compare

match when downcounting.

Table 54. Clock Select Bit Description

CS22

CS21

CS20

Description

No clock source (Timer/Counter stopped).

clkT2S/(No prescaling)

clk

T2S/8 (From prescaler)

clk

T2S/32 (From prescaler)

clk

T2S/64 (From prescaler)

clk

T2S/128 (From prescaler)

clk

2S/256 (From prescaler)

clkT2S/1024 (From prescaler)

Bit

765

432

TCNT2[7:0]

TCNT2

Read/Write

R/W

Initial Value

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