ATmega16 datasheet(111/315 Pages) ATMEL

111 / 315 page

111

ATmega16(L)

2466E–AVR–10/02

8-bit Timer/Counter2

with PWM and

Asynchronous

Operation

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The

main features are:

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)

• Allows clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the

actual placement of I/O pins, refer to “Pinouts ATmega16” on page 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

page 121.

Figure 53. 8-bit Timer/Counter Block Diagram

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers.

Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag

shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously

clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous

operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select

logic block controls which clock source the Timer/Counter uses to increment (or decre-

ment) its value. The Timer/Counter is inactive when no clock source is selected. The

output from the Clock Select logic is referred to as the timer clock (clk

T2).

Timer/Counter

TCNTn

Waveform

Generation

OCn

= 0

Control Logic

= 0xFF

TOP

BOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCn

(Int.Req.)

Synchronization Unit

OCRn

TCCRn

ASSRn

Status flags

clk

I/O

clk

ASY

Synchronized Status flags

asynchronous mode

select (ASn)

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clk

I/O

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