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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AX88140AP датащи(PDF) 20 Page - ASIX Electronics Corporation |
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AX88140AP датащи(HTML) 20 Page - ASIX Electronics Corporation |
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20 / 46 page  AX88140A PRELIMINARY ASIX ELECTRONICS CORPORATION 20 4.0 Registers Operation 1. The REGs are quad-word aligned, 32-bits long, and must be accessed using long-word instruction with quad-word aligned addresses only. 2. Reserved bits should be written with 0.; Reserved bits are UNPREDICTABLE on read access. 3. Retries on second data transactions occur in response to burst accesses. 4.1 Registers Mapping REGISTER MEANING OFFSET FROM REG BASE ADDRESS (CBIO,CBMA) REG0 BUS MODE 00H REG1 TRANSMIT POLL DEMAND 08H REG2 RECEIVE POLL DEMAND 10H REG3 RECEIVE LIST BASE ADDRESS 18H REG4 TRANSMIT LIST BASE ADDRESS 20H REG5 STATUS 28H REG6 OPERATION MODE 30H REG7 INTERRUPT ENABLE 38H REG8 MISSED FRAME AND OVERFLOW COUNTER 40H REG9 SERIAL ROM, AND MII MANAGEMENT 48H REG10 - 50H REG11 GENERAL-PURPOSE TIMER 58H REG12 GENERAL-PURPOSE PORT 60H REG13 FILTERING BUFFER INDEX 68H REG14 FILTERING BUFFER DATA 70H Tab - 14 Command and Status Register Mapping |
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