AX88140AP datasheet(14/46 Pages) ASIX

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AX88140A

PRELIMINARY

ASIX ELECTRONICS CORPORATION

2.3 Boot ROM , Serial ROM , General-purpose signals group

SIGNAL

TYPE

NUMBER

FOR 160 PIN

NUMBER

FOR 144 PIN

DESCRIPTION

BR_A<0>

112

102

Boot ROM address line bit 0.

BR_A<1>

113

103

Boot ROM address line bit 1. This pin also latches the boot ROM

address and control lines by the two external latches.

BR_AD<7>

BR_AD<6>

BR_AD<5>

BR_AD<4>

BR_AD<3>

BR_AD<2>

BR_AD<1>

BR_AD<0>

I/O

110,

109,

106,

105,

104,

103,

102,

101

100,

99,

96,

95,

94,

93,

92,

Boot ROM address and data multiplexed lines bits 7 through 0. In

the first of two consecutive address cycles, these lines contain the

boot ROM address bits 9 through 2; followed by boot ROM

address bits 17 through 10 in the second cycle. During the data

cycle, bits 7 through 0 contain data.

BR_CE#

111

101

Boot ROM chip enable.

SR_CK

Serial ROM clock signal.

SR_CS

Serial ROM chip-select signal.

SR_DI

Serial ROM data-in signal.

SR_DO

Serial ROM data-out signal.

GENP<7>

GENP<6>

GENP<5>

GENP<4>

GENP<3>

GENP<2>

GENP<1>

GENP<0>

I/O

99,

98,

97,

96,

93,

92,

91,

89,

88,

87,

86,

83,

82,

81,

General-purpose pins can be used by software as either status pins

or control pins. These pins can be configured by software to

perform either input or output functions.

Tab - 2 Boot ROM , Serial ROM , General-purpose signals group

2.4 MII/SYM/SRL interface signals group

SIGNAL

TYPE PIN

NUMBER

FOR 160 PIN

NUMBER

FOR 144 PIN

DESCRIPTION

MCOL

126

112

Collision detected is asserted when detected by an

external physical layer protocol(PHY) device.

MCRS

127

113

Carrier sense is asserted by the PHY when the media

is active.

MRXDV

125

111

Data valid is asserted by an external PHY when

receive data is present on the MRXD/SYRXD lines

and is deasserted at the end of the packet. This signal

should be synchronized with the

MRCLK/SYMRCLK signal.

MRXERR

124

110

Receive error asserts when a data decoding error is

detected by an external PHY device. This signal is

synchronized to MRCLK/SYMRCLK and can be

asserted for a minimum of one receive clock. When

asserted during a packet reception, it sets the cyclic

redundancy check(CRC) error bit in the receive

descriptor (RDESO).

MDC

116

106

MII management data clock is sourced by the

AX88140A to the PHY devices as a timing reference

for the transfer of information on the MII_MDIO

signal.

MDIO

I/O

115

105

MII management data input/output transfers control

information and status between the PHY and the

AX88140A.

MII/SRL

147

133

Indicates the selected port: SRL or MII/SYM. When

asserted, the MII/SYM port is active. When

deasserted, the SRL port is active.

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