®

AS4LC8M8S0

AS4LC4M16S0

7/5/00

ALLIANCE SEMICONDUCTOR

9

AC parameters common to all waveforms (continued)

Notes

1

Minimum clock cycles = (Minimum time / clock cycle time) rounded up.

2

Minimum delay required to complete write.

3

Column address change allowed every cycle.

4

Parameters dependent on CAS latency.

5If clock rising time

> 1ns, (tr/2-0.5)ns should be added to parameter.

6

If (tr and tf)

> 1ns, [(tr+tf)/2-1]ns should be added to parameter.

7

Outputs measured at 1.5V with 50pF load only without resistive termination.

Burst sequence

(BL = 4)

Burst sequence

(BL = 8)

Sym

Parameter

CAS

latency

-75

-8

-10 F

-10

Unit

Notes

Min Max

Min

Max

Min

Max

Min

Max

DQM to input data delay

1

–

1

–

1

–

1

–

CLK

0

–

0

–

0

–

0

–

CLK

DQM to data high Z during

reads

2

–

2

–

2–

2–

CLK

Write command to input data

delay

0

–

0

–

0–

0–

CLK

Data-in to active command

5

–

5

–

5

–

5

–

CLK

Load mode register to active/

refresh command

1

–

1

–

1–

1–

CLK

Data-out high Z from

precharge/burst stop command

33

–

3

–

3

–

3

–

CLK

4

22

–

2

–

2

–

2

–

CLK

4

CKE to CLOCK disable or power-

down entry mode

1

–

1

–

1–

1–

CLK

CKE to clock enable or power-

down exit mode

1

–

1

–

1–

1–

CLK

Initial address

Sequential

Interleave

A1

A0

0

0

0

123

0123

0

1

1

230

1032

1

0

2

301

2301

1

1

3

012

3210

Initial address

Sequential

Interleave

A2

A1

A0

0

0

0

0123456701234567

0

0

1

1234567010325476

0

1

0

2345670123016745

0

1

1

3456701232107654

1

0

0

4567012345670123

1

0

1

5670123454761032

1

1

0

6701234567452301

1

1

1

7012345676543210