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AS4LC8M8S0 датащи(PDF) 7 Page - Alliance Semiconductor Corporation

номер детали AS4LC8M8S0
подробное описание детали  3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
PDF  24 Pages
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производитель  ALSC [Alliance Semiconductor Corporation]
домашняя страница  https://www.alliancememory.com
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AS4LC8M8S0 датащи(HTML) 7 Page - Alliance Semiconductor Corporation

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AS4LC8M8S0
AS4LC4M16S0
7/5/00
ALLIANCE SEMICONDUCTOR
7
IDD specifications and conditions
(0
° C ≤ T
A ≤ 70° C, VDD, VDDQ = +3.3V ± 0.3V)
Notes
1IDD specifications are tested after proper initialization of the device.
2IDD is dependent on output loading and clock cycle time. Values are specified with minimum cycle time and outputs open.
3IDD tests have VIL = 0V and VIH = 3V.
4IDD current will decrease at lower CAS latencies. This is because the lower the latency, the lower the clock cycle time.
5
Address transitions average one transition every two clock cycles.
Parameter
Symbol
Max
Units
Notes
–75
–8
–10F/10
Operating current: active mode; burst = 2; READ or WRITE;
tRC = tRC(min); CAS latency = 3
IDD1
115
95
95
mA
4, 5
Standby current: power-down mode; all banks idle;
CKE = low
IDD2
22
2
mA
4,5
Standby current: active mode; CKE = high; CS# = high; all
banks active after tRCD met; no accesses in progress
IDD3
45
35
35
mA
4, 5
Operating current: burst mode; continuous burst; READ or
WRITE; all banks active; CAS latency = 3
IDD4
140
130
120
mA
4,5
Auto refresh current: CKE = high;
CS# = high
tRFC = tRFC(min);
CL = 3
IDD5
210
210
190
mA
4, 5
tRFC = 15.625ms;
CL = 3
IDD6
50
50
40
mA
4,5
Self-refresh current: CKE
≤ 0.2V
IDD7
11
1
mA
4,5



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