Z86L71 datasheet(47/61 Pages) ZILOG

47 / 61 page

Z86L70/71/75/C71

Zilog

IR/Low-Voltage Microcontroller

DS97LVO0500

P R E L I M I N A R Y

1-47

Watch-Dog Timer Mode Register (WDTMR). The WDT

is a retriggerable one-shot timer that resets the Z8 if it

reaches its terminal count. The WDT must initially be en-

abled by executing the WDT instruction and refreshed on

subsequent executions of the WDT instruction. The WDT

circuit is driven by an on-board RC oscillator or external

oscillator from the XTAL1 pin. The WDT instruction affects

the Zero (Z), Sign (S), and Overflow (V) flags.

The POR clock source is selected with bit 4 of the WDT

time-out period. Bit 2 determines whether the WDT is ac-

tive during HALT and Bit 3 determines WDT activity during

STOP. Bits 5 through 7 are reserved (Figure 37). This reg-

ister is accessible only during the first 64 processor cycles

(128 XTAL clocks) from the execution of the first instruc-

tion after Power-On-Reset, Watch-Dog Reset, or a Stop-

Mode Recovery (Figure 40). After this point, the register

cannot be modified by any means, intentional or other-

wise. The WDTMR cannot be read and is located in Bank

F of the Expanded Register Group at address location

0FH. It is organized as follows:

Figure 37. Watch-Dog Timer Mode Register

(Write Only)

WDTMR (0F) 0F

WDT TAP

INT RC OSC External Clock

5 ms

256 TpC

10 ms

512 TpC

20 ms

1024 TpC

80 ms

4096 TpC

WDT During HALT

0 OFF

1 ON

WDT During STOP

0 OFF

1 ON

XTAL1/INT RC Select for WDT

0 On-Chip RC

1 XTAL

Reserved (Must be 0)

* Default Setting After Reset

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