Z86L71 datasheet(30/61 Pages) ZILOG

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Z86L70/71/75/C71

IR/Low-Voltage Microcontroller

Zilog

1-30

P R E L I M I N A R Y

DS97LVO0500

FUNCTIONAL DESCRIPTION (Continued)

Input Circuit

The edge detector monitors the input signal on P31 or P20.

Based on CTR1 D5-D4, a pulse is generated at the Pos

Edge or Neg Edge line when an edge is detected. Glitches

in the input signal which have a width less than specified

(CTR1 D3, D2) are filtered out.

T8 Transmit Mode

When T8 is enabled, the output of T8 depends on CTR1,

D1. If it is 0, T8_OUT is 1. If it is 1, T8_OUT is 0.

When T8 is enabled, the output T8_OUT switches to the

initial value (CTR1 D1). If the initial value (CTR1 D1) is 0,

TC8L is loaded, otherwise TC8H is loaded into the

counter. In Single-Pass Mode (CTR0 D6), T8 counts down

to 0 and stops, T8_OUT toggles, the time-out status bit

(CTR0 D5) is set, and a time-out interrupt can be generat-

ed if it is enabled (CTR0 D1) (Figure 22). In Modulo-N

Mode, upon reaching terminal count, T8_OUT is toggled,

but no interrupt is generated. Then T8 loads a new count

(if the T8_OUT level now is 0), TC8L is loaded; if it is 1,

TC8H is loaded. T8 counts down to 0, toggles T8_OUT,

sets the time-out status bit (CTR0 D5) and generates an

interrupt if enabled (CTR0 D1) (Figure 23). This completes

one cycle. T8 then loads from TC8H or TC8L according to

the T8_OUT level, and repeats the cycle.

The user can modify the values in TC8H or TC8L at any

time. The new values take effect when they are loaded.

Care must be taken not to write these registers at the time

the values are to be loaded into the counter/timer, to en-

sure known operation. An initial count of 1 is not al-

lowed (a non-function will occur). An initial count of 0

will cause TC8 to count from 0 to %FF to %FE (Note, % is

used for hexadecimal values). Transition from 0 to %FF is

not a time-out condition.

Note: Using the same instructions for stopping the

counter/timers and setting the status bits is not rec-

ommended. Two successive commands, first stopping

the counter/timers, then resetting the status bits is neces-

sary. This is required because it takes one counter/timer

clock interval for the initiated event to actually occur.

Figure 19. T8_OUT in Single-Pass Mode

TC8H Counts

“Counter Enable” Command,

T8_OUT Switches To Its

Initial Value (CTR1 D1)

T8_OUT Toggles,

Time-Out Interrupt

Figure 20. T8_OUT in Modulo-N Mode

“Counter Enable” Command,

T8_OUT Switches To Its

Initial Value (CTR1 D1)

T8_OUT Toggles

T8_OUT

TC8L

TC8H

TC8L

TC8H

TC8L

Time-Out Interrupt

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