CS4328 datasheet(23/31 Pages) CIRRUS

23 / 31 page

The CS4328 supports four serial data input for-

mats. The selection of which is made via the

digital input format pins DIF0 and DIF1. The

different formats control the relationship of L/R

to SDATA and the edge of SCLK used to latch

the data. Consult the CS4328 data sheet for an

explanation of the different formats.

System Timing

The master clock input to the CS4328 can be

provided by several sources. JP3 selects the

source of the master clock that is to be supplied

to the XTI pin of the converter.

When EXT

CLK is selected, the master clock is provided by

one of two sources. The 12.288 MHz clock sig-

nal provided by U8 can be used as the master

clock for both the CS4328 and the external sys-

tem that provides the serial data to the board.

The other option is for a master clock that is

synchronized to the external serial data coming

into the board, be used as the master clock for

the CS4328 as well.

However, if an external

LRCK

BICK

SDATAI

XTI

XTO

RST

CKS

DIFO

DIFI

VREF

AOUTR

AOUTL

CALI

CALO

CMPI

CMPO

AGND3

AGND2

AGND1

VA+

ACKI

ACKO

VD+

R11

47k

Ω

TST DGND

C19

10 nF NPO

C16

0.1 uF

C17

10 uF

Ω

C18

10 nF NPO

Ω

VA-

-5V Analog,

VA-

+5V Analog,

VA+

C24

1.0 uF

C23

0.1 uF

C22

0.1 uF

AOUTL

AOUTR

VD+

1 uF

C26

0.1 uF

C25

U3, Pin 3

U3, Pin 6

U3, Pin 8

U3, Pin 11

L/R SCLK SDATA MCLK

From

Reset

Circuit

CS4328

C20

1.0 uF

C21

0.1 uF

JP2

Figure 2. CS4328 DAC Connections

Position

Input Option Selected

EXT CLK

SDATA,SCLK, L/R provided

by an external source.

8412

SDATA,SCLK, L/R provided

by the CS8412

Table 1. JP3 Selectable Options

CDB4328

DS62DB2

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