поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

CS4328 датащи(PDF) 22 Page - Cirrus Logic

номер детали CS4328
подробное описание детали  18-Bit, Stereo D/A Converter for Digital Audio
PDF  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4328 датащи(HTML) 22 Page - Cirrus Logic

Back Button CS4328 Datasheet HTML 18Page - Cirrus Logic CS4328 Datasheet HTML 19Page - Cirrus Logic CS4328 Datasheet HTML 20Page - Cirrus Logic CS4328 Datasheet HTML 21Page - Cirrus Logic CS4328 Datasheet HTML 22Page - Cirrus Logic CS4328 Datasheet HTML 23Page - Cirrus Logic CS4328 Datasheet HTML 24Page - Cirrus Logic CS4328 Datasheet HTML 25Page - Cirrus Logic CS4328 Datasheet HTML 26Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 31 page
background image
Power Supply Circuitry
Figure 1 shows the evaluation board power sup-
ply circuitry. Power is supplied to the evaluation
board by five binding posts. The +5 V analog
power supply inputs of the converter are derived
from + 15 V using the voltage regulators U5 and
U6. The +5 V digital supply for the converter
and the discrete logic on the board is provided
by the +5 V and DGND binding posts. D1, D2,
and D3 are transient suppressors which also pro-
vide protection from incorrectly connected
power supply leads.
C1-C8 provide general
power supply filtering for the analog supplies.
As shown in Figure 2, C20-C24 provide local-
ized decoupling for the converter VA+ and VA-
pins. Note that C22 is connected between VA-
and VA+ and not VA- and AGND. The evalu-
ation board uses both an analog and a digital
ground plane which are connected at J1. This
ground plane arrangement isolates the board’s
digital logic from the analog circuitry.
Offset Calibration & Reset Circuitry
Figure 1, shows the offset calibration circuit pro-
vided on the evaluation board. Upon power-up,
this circuit provides a pulse on the Digital to
Analog Converter’s RST pin initiating an offset
calibration cycle. Pressing and releasing S2 also
initiates an offset calibration cycle.
Serial Data Interface
Figure 1 shows that there are two options for in-
puting serial data into the CS4328. Serial data
can be provided via the SDATA BNC connector
on the evaluation board.
BNC connectors for
SCLK, the serial data input clock, and L/R, the
clock that defines the channel and delineates the
data, are also provided on the evaluation board.
This information can also be provided by the on-
board CS8412.
JP3 selects the source of
SDATA, SCLK, and L/R that will be provided to
the converter.
JP3 selections are shown in Ta-
ble 1.
C6
C7
C5
C8
0.22 uF
0.47 uF
J1
+ C3
47 uF
C4
+
47 uF
0.22 uF
OUT
COM
U5
78L05
IN
D3
D2
0.47 uF
C2
+ C1
47 uF
0.1 uF
D1
+15V
-15V
+5V
79L05
U6
COM
IN
OUT
DGND
AGND
VA+
VA-
VD+
D1 = P6KE-6V8P from Thomson
D2 = D3 = 1N6276A 1.5KE
AGND
DGND
VD+
10k
C15
0.1uF
D13
1N148
S2
CAL
R4
4
3
U7B
74HC14
6
5
U7C
RST
CS4328
Figure 1. Power Supply and Reset Circuitry
CDB4328
22
DS62DB2



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com