CS4328 datasheet(14/31 Pages) CIRRUS

14 / 31 page

capacitor, where the polarity of each packet is

controlled by the 1-bit signal.

The result is a

1-bit D/A conversion process that is very insensi-

tive to clock jitter. This is a major improvement

over previous generations of 1-Bit D/A convert-

ers where the magnitude of charge in the D/A

process is determined by switching a current ref-

erence for a period of time defined by periods of

the master clock.

The final stage of the CS4328 is made up of a

5th order switched-capacitor low pass filter and a

2nd order continuous time filter. The switched-

capacitor filter eliminates out-of-band energy re-

su lting from the n o ise sh ap ing proces s

(Figure 25). The switched-capacitor stage scales

with the master clock signal being applied to the

CS4328. The final stage is a 2nd order continu-

ous time filter that eliminates high frequency

energy that appears at multiples of the 64

× Fs

sample rate (Figure 26).

Figures 27-30 are computer simulations of the

combined response of the CS4328 digital and

analog filters with an input word rate of 48 kHz.

Figure 27 shows the individual and combined

phase response of the CS4328 filters. Notice the

digital filter equalization of the analog filter to

produce a linear phase response.

Figures 28-30 are plots of the CS4328 magni-

tude response.

Frequency (kHz)

-20

-16

-12

-8

-4

Analog Filter

Digital Filter

Total Phase

Figure 27. Deviation From Linear Phase

f (kHz)

64Fs

(dB)

Figure 25. Spectrum After Switched-Capacitor Filter

f (kHz)

(dB)

Figure 26. Spectrum After Continuous Time Filter

CS4328

DS62F3

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