PIC17C44-08SLASHP datasheet(40/240 Pages) MICROCHIP

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PIC17C4X

DS30412C-page 40

6.4.1

INDIRECT ADDRESSING REGISTERS

The PIC17C4X has four registers for indirect address-

ing. These registers are:

• INDF0 and FSR0

• INDF1 and FSR1

Registers INDF0 and INDF1 are not physically imple-

mented. Reading or writing to these registers activates

indirect addressing, with the value in the correspond-

ing FSR register being the address of the data. The

FSR is an 8-bit register and allows addressing any-

where in the 256-byte data memory address range.

For banked memory, the bank of memory accessed is

speciﬁed by the value in the BSR.

If ﬁle INDF0 (or INDF1) itself is read indirectly via an

FSR, all '0's are read (Zero bit is set). Similarly, if

INDF0 (or INDF1) is written to indirectly, the operation

will be equivalent to a NOP, and the status bits are not

affected.

6.4.2

INDIRECT ADDRESSING OPERATION

The indirect addressing capability has been enhanced

over that of the PIC16CXX family. There are two con-

trol bits associated with each FSR register. These two

bits conﬁgure the FSR register to:

• Auto-decrement the value (address) in the FSR

after an indirect access

• Auto-increment the value (address) in the FSR

after an indirect access

• No change to the value (address) in the FSR after

an indirect access

These control bits are located in the ALUSTA register.

The FSR1 register is controlled by the FS3:FS2 bits

and FSR0 is controlled by the FS1:FS0 bits.

When using the auto-increment or auto-decrement

features, the effect on the FSR is not reﬂected in the

ALUSTA register. For example, if the indirect address

causes the FSR to equal '0', the Z bit will not be set.

If the FSR register contains a value of 0h, an indirect

read will read 0h (Zero bit is set) while an indirect write

will be equivalent to a NOP (status bits are not

affected).

Indirect addressing allows single cycle data transfers

within the entire data space. This is possible with the

use of the MOVPF and MOVFP instructions, where either

'p' or 'f' is speciﬁed as INDF0 (or INDF1).

If the source or destination of the indirect address is in

banked memory, the location accessed will be deter-

mined by the value in the BSR.

A simple program to clear RAM from 20h - FFh is

shown in Example 6-1.

EXAMPLE 6-1:

INDIRECT ADDRESSING

MOVLW

0x20

;

MOVWF

FSR0

; FSR0 = 20h

BCF

ALUSTA, FS1

; Increment FSR

BSF

ALUSTA, FS0

; after access

BCF

ALUSTA, C

; C = 0

MOVLW

END_RAM + 1

;

CLRF

INDF0

; Addr(FSR) = 0

CPFSEQ

FSR0

; FSR0 = END_RAM+1?

GOTO

; NO, clear next

; YES, All RAM is

; cleared

6.5

Table Pointer (TBLPTRL and

TBLPTRH)

File registers TBLPTRL and TBLPTRH form a 16-bit

pointer to address the 64K program memory space.

The table pointer is used by instructions TABLWT and

TABLRD

The TABLRD and the TABLWT instructions allow trans-

fer of data between program and data space. The table

pointer serves as the 16-bit address of the data word

within the program memory. For a more complete

description of these registers and the operation of Table

Reads and Table Writes, see Section 7.0.

6.6

Table Latch (TBLATH, TBLATL)

The table latch (TBLAT) is a 16-bit register, with

TBLATH and TBLATL referring to the high and low

bytes of the register. It is not mapped into data or pro-

gram memory. The table latch is used as a temporary

holding latch during data transfer between program and

data memory (see descriptions of instructions TABLRD,

TABLWT

, TLRD and TLWT). For a more complete

description of these registers and the operation of Table

Reads and Table Writes, see Section 7.0.

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