PIC16F84A-10SLASHP datasheet(23/124 Pages) MICROCHIP

23 / 124 page

PIC16F8X

DS30430C-page 23

5.2

PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. A '1' on

any bit in the TRISB register puts the corresponding

output driver in a hi-impedance mode. A '0' on any bit

in the TRISB register puts the contents of the output

latch on the selected pin(s).

Each of the PORTB pins have a weak internal pull-up.

A single control bit can turn on all the pull-ups. This is

done by clearing the RBPU (OPTION_REG<7>) bit.

The weak pull-up is automatically turned off when the

port pin is conﬁgured as an output. The pull-ups are

disabled on a Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

conﬁgured as an output is excluded from the interrupt

on change comparison). The pins value in input mode

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of the pins are

OR’ed

together

generate

the

port

change interrupt.

FIGURE 5-3:

BLOCK DIAGRAM OF PINS

RB7:RB4

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

Read (or write) PORTB. This will end the mis-

match condition.

Clear ﬂag bit RBIF.

A mismatch condition will continue to set the RBIF bit.

Reading PORTB will end the mismatch condition, and

allow the RBIF bit to be cleared.

This interrupt on mismatch feature, together with

software conﬁgurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression (see AN552 in the

Embedded Control Handbook).

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 5-4:

BLOCK DIAGRAM OF PINS

RB3:RB0

RBPU(1)

Data Latch

From other

VDD

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

Note

1: TRISB = '1' enables weak pull-up

(if RBPU = '0' in the OPTION_REG register).

2: I/O pins have diode protection to VDD and VSS.

I/O

pin(2)

Note 1: For a change on the I/O pin to be

recognized, the pulse width must be at

least TCY (4/fOSC) wide.

RBPU(1)

I/O

pin(2)

Data Latch

VDD

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak

pull-up

RD Port

RB0/INT

TTL

Input

Buffer

Schmitt Trigger

Buffer

TRIS Latch

Note

1: TRISB = '1' enables weak pull-up

(if RBPU = '0' in the OPTION_REG register).

2: I/O pins have diode protection to VDD and VSS.

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