PIC16F84A-10SLASHP datasheet(47/124 Pages) MICROCHIP

47 / 124 page

PIC16F8X

DS30430C-page 47

8.9

Interrupts

The PIC16F8X has 4 sources of interrupt:

• External interrupt RB0/INT pin

• TMR0 overﬂow interrupt

• PORTB change interrupts (pins RB7:RB4)

• Data EEPROM write complete interrupt

The interrupt control register (INTCON) records

individual interrupt requests in ﬂag bits. It also contains

the individual and global interrupt enable bits.

The global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. Bit GIE is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which

re-enable interrupts.

The RB0/INT pin interrupt, the RB port change inter-

rupt and the TMR0 overﬂow interrupt ﬂags are con-

tained in the INTCON register.

When an interrupt is responded to; the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. For external interrupt events, such as the

RB0/INT pin or PORTB change interrupt, the interrupt

latency will be three to four instruction cycles. The exact

latency depends when the interrupt event occurs

(Figure 8-17). The latency is the same for both one and

two cycle instructions. Once in the interrupt service

routine the source(s) of the interrupt can be determined

by polling the interrupt ﬂag bits. The interrupt ﬂag bit(s)

must be cleared in software before re-enabling

interrupts to avoid inﬁnite interrupt requests.

FIGURE 8-16: INTERRUPT LOGIC

Note 1: Individual interrupt ﬂag bits are set

regardless

the

status

their

corresponding mask bit or the GIE bit.

RBIF

RBIE

T0IF

T0IE

INTF

INTE

GIE

EEIE

Wake-up

(If in SLEEP mode)

Interrupt to CPU

EEIF

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