8

6

5

7

1

3

4

2

GND

DELAY

SENSE

SD

ERROR

POR

+

-

GND

DELAY

2.2 PA

+

-

SENSE

SD

ERROR

1.2V

6 M:

RFB2

RFB1

0.5V

OFF

ON

LP3997

SNVS272B – MAY 2004 – REVISED MAY 2013

www.ti.com

Functional Block Diagram

Pin Descriptions

Pin No.

Name

Description

1

Noise bypass pin. For low noise applications a 0.1µF or larger ceramic capacitor should be connected from

this pin to ground. This will also improve PSSR.

2

DELAY

A capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (pin

7) output. See Applications Information.

3

GND

4

5

6

SENSE

as possible.

7

ERROR

voltage. This pin also provides a power-on-reset signal if a capacitor is connected to the DELAY pin.

8

SD

Shutdown. Disables the regulator when less than 0.4V is applied. Enables the regulator when greater than

0.9V. The Shutdown pin is pulled down internally by a 6M

Ω resistor.

Connection Diagram

8-Lead VSSOP

Package Number DGK

2

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