RF69 datasheet(48/81 Pages) ETC2

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RF69

Page 47

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(NRZ)

Rx DATA

Bit N-x =

Sync_value[x]

Bit N-1 =

Sync_value[1]

Bit N =

Sync_value[0]

DCLK

SyncAddressMatch

Figure 28. Sync Word Recognition

During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and

the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync

word.

When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be

processed accordingly.

SyncAddressMatch is cleared when leaving Rx or FIFO is emptied.

5.2.3.2. Configuration

 Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. In Packet mode

this field is also used for Sync word generation in Tx mode.

 Error tolerance: The number of errors tolerated in the Sync word recognition can be set from 0 to 7 bits to via

SyncTol.

 Value: The Sync word value is configured in SyncValue(63:0). In Packet mode this field is also used for Sync word

generation in Tx mode.

Note

SyncValue choices containing 0x00 bytes are not allowed

5.2.4. Packet Handler

The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5.

5.2.5. Control

The control block configures and controls the full chip's behavior according to the settings programmed in the configuration

registers.

5.3. Digital IO Pins Mapping

Six general purpose IO pins are available on the RF69, and their configuration in Continuous or Packet mode is

controlled through RegDioMapping1 and RegDioMapping2.

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