RF69 datasheet(18/81 Pages) ETC2

номер детали	RF69

подробное описание детали	Low Power Integrated UHF Transceiver with On-Chip 20dBm PA

PDF	81 Pages

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RF69

Page 18

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3.2.4. Lock Time

PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency, frequency step, etc.

When using the built-in sequencer, the RF69 optimizes the startup time and automatically starts the receiver or the

transmitter when the PLL has locked. To manually control the startup time, the user should either wait for TS_FS max given

in the specification, or monitor the signal PLL lock detect indicator, which is set when the PLL has is within its locking

range.

When performing an AFC, which usually corrects very small frequency errors, the PLL response time is approximately:

In a frequency hopping scheme, the timings TS_HOP given in the table of specifications give an order of magnitude for the

expected lock times.

3.2.5. Lock Detect Indicator

A lock indication signal can be made available on some of the DIO pins, and is toggled high when the PLL reaches its

locking range. Please refer to Table 21 and Table 22 to map this interrupt to the desired pins.

Note

The lock detect block may indicate an unlock condition (signal toggling low) when the transmitter is FSK modulated

with large frequency deviation settings.

RF69 датащи(PDF) 18 Page - List of Unclassifed Manufacturers