RF65 datasheet(37/72 Pages) ETC2

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Page 37

RF65

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ADVANCED COMMUNICATIONS & SENSING

DATASHEET

5. Data Processing

5.1. Overview

5.1.1. Block Diagram

Figure below illustrates the RF65 data processing circuit. Its role is to interface the data from the demodulator and the uC

access points (SPI and DIO pins). It also controls all the configuration registers.

The circuit contains several control blocks which are described in the following paragraphs.

CONTROL

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

Data

SYNC

RECOG.

PACKET

HANDLER

FIFO

(+SR)

SPI

NSS

SCK

MOSI

MISO

Potential datapaths (data operation mode dependant)

Figure 20. RF65 Data Processing Conceptual View

The RF65 implements several data operation modes, each with their own data path through the data processing section.

Depending on the data operation mode selected, some control blocks are active whilst others remain disabled.

5.1.2. Data Operation Modes

The RF65 has two different data operation modes selectable by the user:



Continuous mode: each bit received is accessed in real time at the DIO2/DATA pin. This mode may be used if adequate

external signal processing is available.



Packet mode (recommended): user only retrieves payload bytes from the FIFO. The packet engine automatically

removes the preamble, checks the Sync word, performs AES decryption, checks the CRC, and decodes DC-free

schemes if enabled. The uC processing overhead is hence significantly reduced compared to Continuous mode.

Depending on the optional features activated (CRC, AES, etc) the maximum payload length is limited to FIFO size, 255

bytes or unlimited.

Each of these data operation modes is described fully in the following sections.

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