PIC16C72-04SLASHSP datasheet(45/124 Pages) MICROCHIP

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PIC16C72 Series

Preliminary

DS39016A-page 45

8.3.1

OPERATION OF SSP MODULE IN SPI

MODE - PIC16CR72

A block diagram of the SSP Module in SPI Mode is

shown in Figure 8-6.

The SPI mode allows 8-bits of data to be synchro-

nously transmitted and received simultaneously. To

accomplish communication, typically three pins are

used:

• Serial Data Out (SDO)

RC5/SDO

• Serial Data In (SDI)

RC4/SDI/SDA

• Serial Clock (SCK)

RC3/SCK/SCL

Additionally a fourth pin may be used when in a slave

mode of operation:

• Slave Select (SS)

RA5/SS/AN4

When initializing the SPI, several options need to be

speciﬁed. This is done by programming the appropriate

control bits in the SSPCON register (SSPCON<5:0>)

and SSPSTAT<7:6>. These control bits allow the fol-

lowing to be speciﬁed:

• Master Operation (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock Edge (Output data on rising/falling edge of

SCK)

• Clock Rate (master operation only)

• Slave Select Mode (Slave mode only)

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON<5>) must be set. To reset or reconﬁgure SPI

mode, clear bit SSPEN, re-initialize the SSPCON reg-

ister, and then set bit SSPEN. This conﬁgures the SDI,

SDO, SCK, and SS pins as serial port pins. For the pins

to behave as the serial port function, they must have

their data direction bits (in the TRISC register) appro-

priately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (master operation) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

• SS must have TRISA<5> set

FIGURE 8-6:

SSP BLOCK DIAGRAM

(SPI MODE)(PIC16CR72)

Note:

When the SPI is in Slave Mode with SS pin

control enabled, (SSPCON<3:0> = 0100)

the SPI module will reset if the SS pin is set

to VDD.

Note:

If the SPI is used in Slave Mode with

CKE = '1', then the SS pin control must be

enabled.

Read

Write

Internal

data bus

RC4/SDI/SDA

RC5/SDO

RA5/SS/AN4

RC3/SCK/

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

shift

clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 output

TCY

Prescaler

4, 16, 64

TRISC<3>

Edge

Select

SCL

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