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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16C745/P датащи(PDF) 20 Page - Microchip Technology |
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PIC16C745/P датащи(HTML) 20 Page - Microchip Technology |
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20 / 158 page  PIC16C745/765 DS41124A-page 20 Advanced Information © 1999 Microchip Technology Inc. Bank 3 180h INDF(3) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h PCL(3) Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 183h STATUS(3) IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 184h FSR(3) Indirect data memory address pointer xxxx xxxx uuuu uuuu 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah PCLATH(1,3) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 18Bh INTCON(3) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 18Ch- 18Fh — Unimplemented — — 190h UIR — — STALL UIDLE TOK_DNE ACTIVITY UERR USB_RST --00 0000 --00 0000 191h UIE — — STALL UIDLE TOK_DNE ACTIVITY UERR USB_RST --00 0000 --00 0000 192h UEIR BTS_ERR OWN_ERR WRT_ERR BTO_ERR DFN8 CRC16 CRC5 PID_ERR 0000 0000 0000 0000 193h UEIE BTS_ERR OWN_ERR WRT_ERR BTO_ERR DFN8 CRC16 CRC5 PID_ERR 0000 0000 0000 0000 194h USTAT — — — ENDP1 ENDP0 IN — — ---x xx-- ---u uu-- 195h UCTRL — — SEO PKT_DIS DEV_ATT RESUME SUSPND — --x0 000- --xq qqq- 196h UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 -000 0000 197h USWSTAT SWSTAT7 SWSTAT6 SWSTAT5 SWSTAT4 SWSTAT3 SWSTAT2 SWSTAT1 SWSTAT0 0000 0000 0000 0000 198h UEP0 — — — — EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000 199h UEP1 — — — — EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000 19Ah UEP2 — — — — EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000 19Bh- 19Fh Reserved Reserved, do not use. 0000 0000 0000 0000 TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from either bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. |
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