PIC16LC71 datasheet(54/176 Pages) MICROCHIP

54 / 176 page

PIC16C71X

DS30272A-page 54

8.4.5

TIME-OUT SEQUENCE

On power-up the time-out sequence is as follows: First

PWRT time-out is invoked after the POR time delay has

expired. Then OST is activated. The total time-out will

vary based on oscillator conﬁguration and the status of

the PWRT. For example, in RC mode with the PWRT

disabled, there will be no time-out at all. Figure 8-11,

Figure 8-12,

and

Figure 8-13

depict

time-out

sequences on power-up.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(Figure 8-12). This is useful for testing purposes or to

synchronize more than one PIC16CXX device operat-

ing in parallel.

Table 8-10 and Table 8-11 show the reset conditions for

some special function registers, while Table 8-12 and

Table 8-13 show the reset conditions for all the

registers.

8.4.6

POWER CONTROL/STATUS REGISTER

(PCON)

The Power Control/Status Register, PCON has up to

two bits, depending upon the device.

Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is

unknown on a Power-on Reset. It must then be set by

the user and checked on subsequent resets to see if bit

BOR cleared, indicating a BOR occurred. The BOR bit

is a "Don’t Care" bit and is not necessarily predictable

if the Brown-out Reset circuitry is disabled (by clearing

bit BODEN in the Conﬁguration Word).

Applicable Devices

710 71 711 715

Applicable Devices

710 71 711 715

Bit1 is POR (Power-on Reset Status bit). It is cleared

on a Power-on Reset and unaffected otherwise. The

user must set this bit following a Power-on Reset.

For the PIC16C715, bit2 is PER (Parity Error Reset). It

is cleared on a Parity Error Reset and must be set by

user software. It will also be set on a Power-on Reset.

For the PIC16C715, bit7 is MPEEN (Memory Parity

Error Enable). This bit reﬂects the status of the MPEEN

bit in conﬁguration word. It is unaffected by any reset of

interrupt.

8.4.7

PARITY ERROR RESET (PER)

The PIC16C715 has on-chip parity bits that can be

used to verify the contents of program memory. Parity

bits may be useful in applications in order to increase

overall reliability of a system.

There are two parity bits for each word of Program

Memory. The parity bits are computed on alternating

bits of the program word. One computation is per-

formed using even parity, the other using odd parity. As

a program executes, the parity is veriﬁed. The even par-

ity bit is XOR’d with the even bits in the program mem-

ory word. The odd parity bit is negated and XOR’d with

the odd bits in the program memory word. When an

error is detected, a reset is generated and the PER ﬂag

bit 2 in the PCON register is cleared (logic ‘0’). This indi-

cation can allow software to act on a failure. However,

there is no indication of the program memory location

of the failure in Program Memory. This ﬂag can only be

set (logic ‘1’) by software.

The parity array is user selectable during programming.

Bit 7 of the conﬁguration word located at address

2007h can be programmed (read as ‘0’) to disable par-

ity. If left unprogrammed (read as ‘1’), parity is enabled.

Applicable Devices

710 71 711 715

TABLE 8-5:

TIME-OUT IN VARIOUS SITUATIONS, PIC16C71

TABLE 8-6:

TIME-OUT IN VARIOUS SITUATIONS, PIC16C710/711/715

Oscillator Conﬁguration

Power-up

Wake-up from SLEEP

PWRTE = 1

PWRTE = 0

XT, HS, LP

72 ms + 1024TOSC

1024TOSC

1024 TOSC

72 ms

—

Oscillator Conﬁguration

Power-up

Brown-out

Wake-up from SLEEP

PWRTE = 0

PWRTE = 1

XT, HS, LP

72 ms + 1024TOSC

1024TOSC

72 ms + 1024TOSC

1024TOSC

72 ms

—

72 ms

—

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