DB929B datasheet(22/51 Pages) CMLMICRO

22 / 51 page

4-Level FSK Modem Data Pump

Page 22 of 50

MX929B PRELIMINARY INFORMATION

www.mxcom.com Tel: 800 638 5577 336 744 5050

Fax: 336 744 5054

Doc. # 20480171.003

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

All trademarks and service marks are held by their respective companies.

4.5.2.19 TSID: Transmit Station ID

This task takes three ID bytes from the Data Block Buffer, calculates and appends the 6-bit CRC0 checksum,

translates the result to 4-level symbols (with FEC) and transmits the resulting 22 symbols preceded and

followed by 'S' symbols.

Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status

4.5.2.20 RESET: Stop any current action

This task takes effect immediately, and terminates any current action (task, AQSC or AQLEV) the modem

may be performing and sets the BFREE bit of the Status Register to '1', without setting the IRQ bit. It should

be used after VDD is applied first to set the modem into a known state.

Note: Due to delays in the RRC filter, it will take several symbol times for any change caused by RESET to

appear at the TXOUT pin.

4.5.2.21 Task Timing

The following table and figures describe the duration of tasks and timing sequences for Tx and Rx operation.

Task

Time

(symbol times)

t1 Modem in idle state. Time from writing first task to application of first

transmit bit to Tx RRC filter

Any

1 to 2

t2 Time from application of first symbol of the task to the Tx RRC

filter until BFREE goes to a logic ‘1’

T24S

TSID

THB/TIB/TLB

T4S

t3 Time to transmit all symbols of the task

T24S/TSID

THB/TIB/TLB

T4S

t4 Max time allowed from BFREE going to a logic '1' (high) for next

task (and data) to be written to modem

T24S

TSID

THB/TIB/TLB

T4S

t5 Time to receive all symbols of task

SFS

SFP

RSID

RHB/RILB

R4S

25 (minimum)

48 (minimum)

t6 Maximum time between first symbol of task entering the de-

interleave

circuit and the task being written to modem

SFS

SFP

RSID

RHB/RILB

R4S

t7 Maximum time from the last bit of the task entering the de interleave

circuit to BFREE going to a logic '1' (high)

Any

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