4-Level FSK Modem Data Pump

Page 5 of 50

MX929B PRELIMINARY INFORMATION

©2001 MX-COM, INC.

www.mxcom.com Tel: 800 638 5577 336 744 5050

Fax: 336 744 5054

Doc. # 20480171.003

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

All trademarks and service marks are held by their respective companies.

Figures

Figure

Page

Figure 1: Block Diagram ................................................................................................................................... 6

Figure 2: Recommended External Components .............................................................................................. 8

Figure 3: Typical Modem

PC connections ...................................................................................................... 10

Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode................................................ 11

Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5) .................. 12

Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5)........... 12

Figure 7: Over-Air Signal Format.................................................................................................................... 15

Figure 8: Alternative Frame Structures........................................................................................................... 16

Figure 9: Transmit Task Overlapping ............................................................................................................. 18

Figure 10: Receive Task Overlapping ............................................................................................................ 19

Figure 11: Transmit Task Timing Diagram..................................................................................................... 23

Figure 12: Receive Task Timing Diagram ...................................................................................................... 23

Figure 13: RRC Low Pass Filter Delay ........................................................................................................... 23

Figure 14: Ideal 'RXEYE' Signal ..................................................................................................................... 27

Figure 15: Typical Data Quality Reading vs S/N............................................................................................. 29

Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 1 ......................................................... 31

Figure 17: Tx Signal Eye TXIMP = 0 .............................................................................................................. 31

Figure 18: Tx Signal Eye TXIMP = 1 .............................................................................................................. 32

Figure 19: Transmit Frame Example Flowchart, Main Program .................................................................... 34

Figure 20: Tx Interrupt Service Routine.......................................................................................................... 35

Figure 21: Receive Frame Example Flowchart, Main Program....................................................................... 37

Figure 22: Rx Interrupt Service routine........................................................................................................... 38

Figure 23: Acquisition Sequence Timing ........................................................................................................ 39

Figure 24: Effect of AC Coupling on BER (without FEC)................................................................................ 40

Figure 25: Decay Time - AC Coupling............................................................................................................ 41

Figure 26: Typical Connections between Radio and MX929B ....................................................................... 42

Figure 27: Received Signal Quality Monitor Flowchart................................................................................... 43

Figure 28:

PC Parallel Interface Timings ........................................................................................................ 47

Figure 29: Typical Bit Error Rate With and Without FEC ............................................................................... 48

Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX929BDW ................................................ 49

Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX929BDS................................................ 49

Figure 32: 24-pin PDIP Mechanical Outline: Order as part no. MX929BP .................................................... 50