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CMX608 датащи(PDF) 43 Page - CML Microcircuits

номер детали CMX608
подробное описание детали  Integrated Input and Output Channel Filters
PDF  70 Pages
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производитель  CMLMICRO [CML Microcircuits]
домашняя страница  http://www.cmlmicro.com
Logo CMLMICRO - CML Microcircuits

CMX608 датащи(HTML) 43 Page - CML Microcircuits

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RALCWI Vocoder
CMX608/CMX618/CMX638
 2014 CML Microsystems Plc
43
D/608_18_38/11
When running the Vocoder in full-duplex mode (CMX638 only), the last bit of the data to be
decoded should be clocked into the device no later than 6ms after the VDA bit is set and (if
enabled) the corresponding IRQN is generated. This will ensure that the decoding and encoding
operations are scheduled correctly. Note that a C-BUS clock of at least 200kHz will be required in
streaming mode for transferring 80ms samples of soft decision encoded data. A higher C-BUS
clock speed is required if the data transfer is done a byte at a time.
The following table shows the frequency and packet size that needs to be written against the
configuration setting:
VCFG Register
Description of packet
DECFRAME
7
6
5
4
3
2
1
0
Byte
Count
Prod.
every
x
x
x
0
0
1
0
1
2400bps 1x20ms frame
6
20ms
x
x
x
0
0
1
1
0
2400bps 2x20ms frames
12
40ms
x
x
x
0
0
1
1
1
2400bps 3x20ms frames
18
60ms
x
x
x
0
0
1
0
0
2400bps 4x20ms frames
24
80ms
x
x
x
0
1
0
0
1
2750bps 1x20ms frame
7
20ms
x
x
x
0
1
0
1
0
2750bps 2x20ms frames
14
40ms
x
x
x
0
1
0
1
1
2750bps 3x20ms frames
21
60ms
x
x
x
0
1
0
0
0
2750bps 4x20ms frames
28
80ms
x
x
1
1
0
1
1
1
2400bps 3x20ms frames
with FEC / Hard bits
27
60ms
x
x
1
1
1
0
1
1
2750bps 3x20ms frames
with FEC / Hard bits
27
60ms
x
x
1
1
0
1
0
0
2400bps 4x20ms frames
with FEC / Hard bits
36
80ms
x
x
1
1
1
0
0
0
2750bps 4x20ms frames
with FEC / Hard bits
36
80ms
x
x
0
1
0
1
1
1
2400bps 3x20ms frames
with FEC / Soft bits
108
60ms
x
x
0
1
1
0
1
1
2750bps 3x20ms frames
with FEC / Soft bits
108
60ms
x
x
0
1
0
1
0
0
2400bps 4x20ms frames
with FEC / Soft bits
144
80ms
x
x
0
1
1
0
0
0
2750bps 4x20ms frames
with FEC / Soft bits
144
80ms
Table 6 Decoder Packet Description
This register is also used for loading blocks of Function Image
™ data. Refer to section 6.7 for
further details.



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