+2.5V to +5.5V, Low-Power, Single/Dual,

8-Bit Voltage-Output DACs in µMAX Package

_______________________________________________________________________________________

5

OUTPUT GLITCH FILTERING

5

µs/div

CS, 5V/div

CODE = 00 hex

_____________________________Typical Operating Characteristics (continued)

SETTLING TIME (RISING)

OUT, 1V/div

2

µs/div

CS, 5V/div

DAC CODE 00 hex to FF hex

______________________________________________________________Pin Description

Ground

1

1

1

GND

DAC A Output Voltage

2

2

—

OUTA

Chip-Select Input. A logic low on CS enables serial data to be

clocked into the input shift register. Programming commands are

executed at CS’s rising edge.

3

3

3

CS

DAC Output Voltage

—

—

2

OUT

Serial-Clock Input. Data is clocked in on SCLK’s rising edge.

5

5

5

SCLK

DAC B Output Voltage

6

7

—

OUTB

Load DAC Input. After CS goes high and if programmed by the

control word, a falling edge on LDAC updates the DAC latch(es).

—

6

6

LDAC

Serial-Data Input. Data is clocked into the 16-bit input shift register on

SCLK’s rising edge.

4

4

4

DIN

Positive Power Supply (+2.5V to +5.5V)

8

8

8

External Reference Voltage Input for DAC(s)

7

—

7

REF

MAX548A

MAX549A

MAX550A

NAME

FUNCTION

PIN