MAX550ACSLASHD datasheet(3/16 Pages) MAXIM

3 / 16 page

+2.5V to +5.5V, Low-Power, Single/Dual,

8-Bit Voltage-Output DACs in µMAX Package

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ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C)

TIMING CHARACTERISTICS

(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Digital inputs switching from 0V to VDD.) (Figure 3) (Note 4)

Note 1: Cold temperature specifications (to -40°C) guaranteed by design using six sigma design limits.

Note 2: Worst-case input resistance at REF occurs at DAC code 55 hex.

Note 3: Worst-case reference input current occurs at DAC code 55 hex.

Note 4: Guaranteed by design. Not production tested.

Note 5: IDD measured with DACs loaded with worst-case DAC code 55 hex.

CS = high, all digital inputs from 0V to VDD

CL = 20pF

To ±1/2LSB, CL = 20pF

V/µs

3.1

µs

1.4

Voltage-Output Settling Time

CONDITIONS

nV-sec

Digital Feedthrough and

Crosstalk

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

Voltage-Output Slew Rate

CL = 20pF

µs

Wake-Up Time at Power-Up

VDD = 2.5V

VDD = 5.5V

Supply Voltage Range

Outputs unloaded, all inputs = GND or VDD

VDD

2.5

5.5

Supply Current

(MAX549A/MAX550A)

Outputs unloaded,

all inputs = GND or

VDD (Note 5)

µA

330

550

IDD

Supply Current (MAX548A)

Outputs unloaded, all inputs = GND or VDD;

VDD = 5.5V

IDD

µA

0.3

VDD = 5.5V

VDD = 2.5V

Shutdown Current

Shutdown mode

µA

0.3

150

250

SCLK Period

tCP

CS High to LDAC Low

tCSLD

MAX548A/MAX550A only

VDD High to CS Low

µs

LDAC Pulse Width Low

tLDAC

MAX548A/MAX550A only

CS Pulse Width High

tCSW

tCSH1

VDD = 5.5V

tDH

CS High to SCLK High Setup

tCSS1

Delay, SCLK High to CS High

VDD = 2.5V

VDD = 5.5V

CS Low to SCLK High Setup

tCSS0

DIN to SCLK High Setup

tDS

DIN to SCLK High Hold

VDD = 2.5V

SCLK Pulse Width Low

tCL

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

SCLK Pulse Width High

tCH

DYNAMIC PERFORMANCE

POWER SUPPLIES

SCLK High to CS Low Hold

tCSH0

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